1. Field of the Invention
The present invention relates to clock generation.
2. Description of Related Art
A clock is a periodic signal that can be used for providing a timing or synchronization among a plurality of circuit elements. Clocks are used in numerous applications. For instance, a clock can be used for a flip-flop circuit, which is an apparatus of data storage that updates the data it stores upon a rising edge of the clock; in this case, the rising edge of the clock defines the timing at which the flip-flop circuit updates the data. In many applications, it is highly desirable to have a clock that has perfect periodicity. For instance, it is highly desirable to have a clock where every two neighboring rising edges are separated by a fixed periodicity in time. Mathematically, the timing of a clock signal forms a sequence, say tn, where n is a time index. An ideal clock would have a timing sequence that can be expressed as follows:tn=nT  (1)where T is the period of the clock signal. In practice, the clock usually contains a “jitter” and the timing sequence will most likely deviate from the form expressed in (1). A timing sequence of a real world clock can be expressed as follows:tn=nT+δn  (2)where δn denotes a clock jitter, i.e. a timing error, at time index n. A clock jitter usually contains two components: a random jitter and a deterministic jitter. The random jitter is a random disturbance to the clock timing due to a random noise; the deterministic jitter is a disturbance to the clock timing that is pre-known or predictable. One example of deterministic jitter is a clock generated from a multiplying delay locked loop (MDLL). For instance, a MDLL comprises a (multiplexed) ring oscillator of oscillation frequency of 1 GHz, and a rising edge of a 200 MHz reference clock is periodically injected into the ring oscillator (via multiplexing), effectively breaking the oscillation and refreshing the clock edge of the ring oscillator once per five clock cycles (here, five is the frequency ratio between 1 GHz and 200 MHz) of the oscillation. Due to a timing mismatch between the multiplying path (for the injection of the rising edge of the 200 MHz clock) and the otherwise oscillation path (for the feedback of the ring oscillator to sustain the oscillation), however, the injection of the rising edge of the 200 MHz reference clock will usually introduce a deterministic jitter to the 1 GHz output of the ring oscillator; that is, there is one remarkable timing error for every five cycles of the 1 GHz clock; the clock cycle that exhibits the remarkable timing error is the clock cycle that occurs coincidentally with the injection of the rising edge of the 200 MHz reference clock. As a result, the 1 GHz clock contains a deterministic jitter that occurs coincidentally with the rising edge of the 200 MHz reference clock. While there are some methods proposed to reduce the deterministic jitter, the methods are complicated and somewhat ad hoc solutions. A solution of interest is using a PLL (phase lock loop) for receiving the 1 GHz clock with the deterministic jitter as an input clock and regenerating accordingly a 1 GHz clock with a smaller deterministic jitter as an output clock. As depicted in FIG. 1, PLL 100 comprises: a phase detector 110 for receiving the input clock and the output clock and outputting a phase error signal; a loop filter 130 for receiving the phase error signal and outputting an oscillator control signal; and a controlled oscillator for receiving the oscillator control signal and generating the output clock. PLL 100 is well known in prior art and thus not explained in detail here. It is well known that, PLL 100 enables the output clock to track a timing of the input clock while performing a low pass filtering on the timing of the input clock so that the output clock contain a much smaller deterministic jitter than that of the input clock, provided a bandwidth of PLL 100 is sufficiently smaller than a bandwidth of the deterministic jitter of the input clock. A smaller bandwidth of the PLL leads to a better suppression of the deterministic jitter of the clock that the PLL receives. However, every PLL comprises a controlled oscillator (e.g., controlled oscillator 140 of PLL 100). The controlled oscillator of the PLL also contributes a random jitter to the output clock that the PLL regenerates. A lower bandwidth (of the PLL) leads to a greater random jitter (in the output clock that the PLL generates). Therefore, there is a tradeoff between the capability of suppressing the deterministic jitter (of the input clock that the PLL receives) and the capability to refrain from introducing random jitter (to the output clock that the PLL regenerates).
Accordingly, what is desired is a method of effectively suppressing a deterministic jitter of a clock signal without introducing much random jitter.